Capacitor-less dynamic random access memory based on a III–V transistor with a gate length of 14 nm

Abstract

Dynamic random access memory (DRAM) cells are commonly used in electronic devices and are formed from a single transistor and capacitor. Alternative approaches, which are based on the floating body effect, have been proposed that could reduce manufacturing complexity and minimize the cell footprint by removing the external capacitor. Such capacitor-less DRAM has been demonstrated in silicon, but the use of other materials, including III–V compound semiconductors, remains relatively unexplored, despite the fact that they could lead to enhanced performance. Here we report capacitor-less one-transistor DRAM cells based on indium gallium arsenide (InGaAs). With our InGaAs on insulator transistors, we demonstrate different current levels for each logic state, and thus successful memory behaviour, down to a gate length of 14 nm. Single-transistor dynamic random access memory (DRAM) cells, created using the III–V compound semiconductor indium gallium arsenide, can be scaled down to a gate length of 14 nm.

Cite this article

Navarro, C., Karg, S., Marquez, C. et al. Capacitor-less dynamic random access memory based on a III–V transistor with a gate length of 14 nm. Nat Electron 2, 412–419 (2019). https://doi.org/10.1038/s41928-019-0282-6

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